The present invention relates to a FIFO (First-in first-out) memory device which is used in digital communication devices and the like, and in particular to a FIFO memory device which is capable of shortening a period of time required for writing or reading a data into or from a FIFO memory device having a plurality of memory means which are cascade-connected with each other.
A read/write operation of such a type of FIFO memory device is carried out as follows: data are sequentially shifted along a cascade connection of memory means such as D-latch circuits in accordance with each clock signal from a memory means from an input side to an output side. For example, in data write mode, a data must be always written into a leading or first memory means of the cascade connection. In other words, after writing a data into the first memory means, it is necessary to sequentially shift data from one memory means to the next memory means, which one memory means is closer to an ending or last memory means in order to shift the data of the first memory means to the second memory means and write a new data into the first memory means. In data read mode, a data in the last memory means is firstly read-out in response to one-clock operation and then a shift operation of the data in each memory means to a respective next memory means responsive to a next one-clock operation is repeated, so that respective data is sequentially shifted to the last memory means.
Although a prior art FIFO memory device such as trade model SN74S225 "asynchronous FIFO memory" commercially available from Texas Instrument Co., Ltd. is known, structure and operation of the above-mentioned type memory device which was manufactured by the present assignee will be described in detail with reference to FIG. 7.
In FIG. 7, reference numerals 61, 62 and 63 denote D-latch circuits on each stage encircled by a dotted line which stores an input data Y including one-bit or plural bits and outputs to the next stage.
Reference numerals 64, 67, 610 denote NAND circuits on each stage. 65, 68 and 611 each denotes a D-flip-flop circuit on each stage. Those NAND and D and R-S flip-flop circuits form a circuit for controlling read and write of three-stages D-latch circuits 61, 62 and 63.
In FIG. 7, in an initial state, that is, in a stage that no data is stored in all D-latch circuits 61, 62 and 63, all R-S flip flop circuit 66, 69 and 612 are in a reset state (an output signal on a Q terminal is on a low level).
All D-flip flop circuits 65, 68 and 611 are in a set state (an output signal on the Q terminal is on a high level). An input signal X is on a low level and an input data is on a high level. External clocks CK are consecutive pulses which are used as synchronization clocks for shifting the data Y to the next stage. Since the data Y is shifted in a synchronization relationship with the external clock CK, the external clocks CK are necessary to be sufficiently faster than the data Y in comparison to write and read.
Now, write operation of the prior art will be described. When the input signal becomes a high level, all input signals to the NAND circuit 64 on a first stage becomes a high level, so that an output signal of the NAND circuit 64 becomes a low level. When a clock signal rises up at this time, an output signal on the Q terminal of the D-flip flop circuit 65 becomes a low level at the rise-up edge of the clock CK.
When the output signal on the Q terminal of the D-flip flop circuit 65 becomes a low level, simultaneously the R-S flip flop 66 is set and the D-latch circuit 61 is enabled.
When the R-S flip flop 66 is set, simultaneously the output signal of a Q terminal becomes low level so that the output signal of the NAND circuit 64 is returned to a high level.
At a second clock, the output signal on the Q terminal of the D-flip flop circuit 65 becomes a high level. Accordingly, the D-latch circuit 61 is disabled. It is necessary for the input signal X to return to a low level by the time of rise-up edge of a third clock for preventing the data Y from being inputted to the D-latch circuit 61 twice.
Operation of the D-latch circuit 61 on the first stage in the above mentioned write operation will be described.
As mentioned above, the D-latch circuit 61 is rendered enable at the rise-up edge of the first clock CK and is rendered disable at the rise-up edge of the second clock CK so that an input data Y is taken to and stored in the D-latch circuit 61.
Therefore, each circuit on the second stage performs the same operation as the corresponding circuit on the first stage since all input signals to the NAND gate 67 on the second stage become high level when the R-S flip flop 66 on the first stage is set.
Since the Q terminal of the D-latch circuit 68 on the second stage (an enabling signal of the latch circuit 62) is connected with a reset terminal R of the R-S flip flop circuit 66 on the first stage, the R-S flip flop circuit 66 is reset when a data held by the D-latch circuit 61 on the first stage is taken and stored in the D-latch 62 on the second stage and the D-latch circuit 61 on the first stage is brought into such a state that it may store a new data.
Accordingly, the input signal Y is sequentially shifted to subsequent stages since corresponding circuits on respective stages are identical with each other.
Now, read operation of the above mentioned prior art will be described. It is assumed that data is stored in all D-latch circuits 61, 62 and 63 and that all the R-S flip flop circuits 66, 69 and 612 are set.
In FIG. 7, when a data held in the D-latch circuit 63 on the final stage is read out and an input signal Z becomes low level, the R-S flip flop circuit 612 on the final stage is reset. When the input signal Z is then returned to high level, the output signal on the Q terminal of the D-flip flop circuit 611 becomes low level at the rise-up edge of the first clock CK.
Accordingly, when the R-S flip flop circuit 612 is set, the D-latch circuit 63 is enabled and the output signal from the NAND circuit 610 is returned to high level. Therefore, the output signal on the Q terminal of the D-flip flop 611 becomes a high level at the rise-up edge of the next clock CK and the D-latch circuit 63 is disabled.
Operation of the D-latch circuit on the final stage in the read operation will be described.
As mentioned above, the D-latch circuit 63 is enabled at the rise-up edge of the first clock CK after the input signal Z has become a high level and the D-latch circuit 63 is disabled at the rise-up edge of the second clock CK. Accordingly, a data held in the D-latch circuit 62 on the previous stage is taken into the D-latch circuit 63 on the final stage and read of the next data becomes possible.
Since the Q terminal (enabling signal of the D-latch circuit 63) of the D flip flop circuit 611 on the final stage is connected with the reset terminal R of the R-S flip flop circuit 69 on the previous stage, the R-S flip flop circuit 69 on the previous stage is rendered reset when the data held in the D-latch circuit 62 on the previous stage is taken into the D-latch circuit 63 on the final stage. Therefore, the same operation is sequentially repeated at previous stages so that the data are shifted to subsequent stages since corresponding circuits on respective stages are identically formed.
However, one cycle and two cycles of an external clock CK are required to shift a data Y through one stage for writing and reading, respectively, in the aforementioned prior art FIFO memory device. Therefore, it is necessary to shift data through several stages until the data may be read after the commencement of the writing of the data if no data is stored so that a period of time, approximately one cycle of an external clock multiplied by the number of stages, is required. A period of time, approximate one cycle of an external clock CK multiplied by the number of stages and by two is required until a new data may be written after one data is read out if data are stored in all stages.
Therefore, the above prior art has a problem that a period of time until read-out becomes possible since writing and a period of time until a new data may be written again since reading out are extended with increase in the number of stages.